1. Technical Field
This disclosure relates to semiconductor memory devices and more particularly, to a flash memory device that is capable of reducing a test time.
2. Description of the Related Art
A flash memory device is a highly integrated information storage device in which write and erase operations can be done on board. A flash memory cell includes one field effect transistor (FET) having a selection gate, a floating gate, a source, and a drain. Any variation of a threshold voltage of the flash memory cell results in a fluctuation of the amount of charges on a floating gate. This fluctuation represents information, which is stored in the flash memory cell. A flash memory device is classified as either a NAND flash memory device or a NOR flash memory device. NAND flash memory devices are typically used as mass data storage devices, and NOR flash memory devices are typically used as information storage devices for high speed data processing.
Generally, a NOR flash memory cell has two states—a programmed state and an erased state. When the NOR flash memory cell is programmed, residual electrons are trapped on a floating gate and a threshold voltage rises. Thus, drain-source current does not flow to a selected flash memory cell. The programmed state of the flash memory cell is referred to as logic “0”. When the flash memory cell is erased, there are a small number of residual electrons on the floating gate and source-drain current flows to the flash memory cell. The erased state of the flash memory cell is referred to as logic “1”.
FIG. 1 is a block/circuit diagram illustrating a conventional NOR flash memory device 100. Referring to FIG. 1, a NOR flash memory device 100 includes an address buffer 110, a row predecoder 120, a row decoder 130, a cell array 140, a column predecoder 150, a column decoder 160, and a sense amplifier 170. In the cell array 140, flash memory cells (not shown) are arranged at the intersections of wordlines WLi and bitlines BLi. The address buffer 110 receives an address signal ADDR from the outside so as to program or erase the flash memory cells and divides a row address RowAdd from a column address ColAdd by means of an output of the address buffer 110. The row predecoder 120 decodes the received row address RowAdd to generate a row selection signal RowSel. The row decoder 130 enables a predetermined wordline WLi in response to the row selection signal RowSel and drives the wordline WLi to a predetermined voltage level according to an operation mode of the flash memory device 100. In a program mode, the wordline WLi is driven to a voltage level of 10V. In an erase mode, the wordline WLi is driven to a voltage level of −10V. In a read mode, the wordline WLi is driven to a voltage level of 4.5V.
The column predecoder 150 decodes the received column address ColAdd to generate column selection signals ColSel1[m:0] and ColSel2[n:0]. The column decoder 160 selects a predetermined bitline BLi in response to the column selection signals ColSel1[m:0] and ColSel2[n:0] and connects a selected bitline BLi with the sense amplifier 170 through a data line DLj(j=0–3). For the convenience of description, 16 bitlines BLi (i=0–15) are described. A first column selection signal ColSel1[m:0] selects four bitlines (e.g., BL0, BL5, BL9, BL12) and a second column selection signal ColSel2[n:0] selects one (e.g., BL0) of the selected four bitlines to connect the selected one bitline with a data line (e.g., DL0).
FIG. 2 is a circuit diagram further illustrating the column predecoder 150 of FIG. 1. Referring to FIG. 2, the column predecoder 150 inputs column addresses ColAdd[3:0] to selectively generate first column selection signals ColSel1[3:0] and second column selection signals ColSel2[3:0]. The first and second column addresses ColAdd[0] and ColAdd[1] are decoded through a decoding block 200 to drive level shifters 202, 204, 206, and 208.
FIG. 3 is a circuit diagram illustrating the level shifters 202, 204, 206, and 208 of FIG. 2. Each of the level shifters 202, 204, 206, and 208 is structured as shown in FIG. 3 and generates a high voltage HV of about 10V as its output OUT in response to a low-level input signal IN. Four transistors in the column decoder 160 corresponding to the first column selection signals ColSel1[0], ColSel1[1], ColSel1[2], and ColSel1[3], respectively, are turned on when a high voltage HV appears as the output OUT of the level shifter 202, 204, 206, or 208, respectively. The third and fourth column addresses ColAdd[2] and ColAdd[3] generate second column selection signals ColSel2[0], ColSel2[1], ColSel2[2], and ColSel2[3] of high voltage HV through a decoding block 210 and level shifters 212, 214, 216, and 218. The second column selection signals ColSel2[0], ColSel2[1], ColSel2[2], and ColSel2[3] of high voltage HV select one of the four bitlines (BLi of FIG. 1). Each bitline BLi is coupled to one of the four transistors that are turned on by an activated first column selection signal ColSel1[0], ColSel1[1], ColSel1[2], or ColSel1[3]. In this way the selected signal is connected with a data line.
FIGS. 4A and 4B are cross-sectional diagrams illustrating the column selection transistors of FIG. 1 and where stresses occur in those transistors. When the flash memory device (100 of FIG. 1) is in the program mode, according to a programming type, a voltage of 5V is applied to a bitline of a selected memory cell and a voltage of 0V is applied to a bitline of an unselected memory cell.
The state of the bias of a transistor MF in a first group of transistors 161 (FIG. 1) coupled to the bitline of the unselected memory cell is described below with reference to FIG. 4A. A high voltage of about 10V is applied to a gate of the transistor MF by a first column selection signal ColSel1[0] that is coupled to the gate. A voltage of 0V is applied to a source of the transistor MF by a bitline BLO. Thus, a voltage of 10V is applied between the gate and the source of the transistor MF, and a voltage of 0V is applied to the data line DL0 of FIG. 1 that is coupled to the unselected memory cell.
The state of the bias of a transistor MS in a second group of transistors 162 (FIG. 1) is described below with reference to FIG. 4B. A high voltage of about 10V is applied to a gate of the transistor MS by a second column selection signal ColSel2[0] that is coupled to the gate of the transistor MS, and a voltage of 0V is applied to a drain of the transistor MS that is connected to the data line DL0. This state is maintained until the program is completed, which leads to increase gate oxide stress of the transistors MF and MS.
Furthermore, when the flash memory device (100 of FIG. 1) is in an erase mode, a voltage of about 9V is applied to a bulk that is coupled to a bitline. In this case, the first and second column selection signals ColSel1[m:0] and ColSel2[n:2] have a voltage of about 0V. Accordingly, a voltage of 0V is applied to the gates of the first group of the transistors 161 and a coupling voltage of 9V is applied to the sources thereof. As a result, gate oxide stress in the first group of transistors 161 occurs.
Over time, oxide stress from repeated program and erase operations may degrade the gate oxide layer to cause the transistor to malfunction. This contributes to faulty operation of the flash memory device. Accordingly, there is a need for a method of detecting a transistor error caused by the degradation of the gate oxide layer.
Since the first and second column selection signals ColSel1[m:0] and ColSel2[n:2] alternately apply a high voltage, it takes a long time to screen the transistor error by applying a stress to the first and second groups of the transistors in the column decoder (160 of FIG. 1). Furthermore, after a stress test, additional procedures such as reiteration of program and read operations must be performed to determine whether transistors in the column decoder have leakage paths caused by gate oxide deterioration and/or breakage. As a result, the test time that is required increases.
Embodiments of the invention address these and other disadvantages of the conventional art.